This invention relates to image sensors, particularly of the type comprising an array of pixels, and each pixel including a photo-responsive diode. The invention also relates to a method of manufacturing such an image sensor.
There is currently much interest in reducing the manufacturing complexity of an image sensor array. For example, an improved yield is obtained if the number of processing steps required for the manufacture of the array is reduced. In the case of an array of pixels formed using thin-film technology, the number of accurate masks which are required in the manufacturing process is of particular importance.
These issues have lead to an interest in diode-based pixel configurations. For example, a known pixel configuration comprises a photodiode and a switching diode in series between respective row and column conductors. There have also been proposals to fabricate a stacked pixel configuration, such as shown in U.S. Pat. No. 4,797,560 which simplifies the mask patterns, and enables a high resolution image sensor to be fabricated.
One problem encountered with thin film diodes is the edge leakage current between the n-type semiconductor and p-type semiconductor material across the edge of the diode structure. This leakage current becomes increasingly significant as the dimensions of the individual pixels are reduced.
This invention seeks to reduce further the complexity of manufacturing a diode-based image sensor array, and also seeks to address the problem of edge leakage current effects in thin film diodes.
According to the invention,, there is provided an image sensor comprising an array of photoresponsive pixels provided on a common substrate, each pixel comprising a photodiode having a first semiconductor region of first doping type, an intrinsic semiconductor region over the first semiconductor region, and a second semiconductor region of second, opposite, doping type, over the intrinsic semiconductor region, characterised in that the intrinsic semiconductor region extends between photodiodes within a group of pixels.
In the description and claims, any reference to each pixel having an associated photodiode should be understood in the context of photodiode layers being shared between pixels. The photodiode of a pixel comprises the photodiode layers over a region of the substrate corresponding to the respective pixel.
There have been proposals to share a semiconductor layer between pixels of a photoconductor type sensor matrix, in which photoconductive semiconductor material is sandwiched between pixel electrodes. U.S. Pat. No. 5,132,541 discloses an arrangement of this type.
In the image sensor of the invention, the intrinsic semiconductor layer of the photodiodes of a group of pixels is shared between those pixels. The shared intrinsic semiconductor layer provides a barrier between the n-type and p-type (the two opposite doping types) semiconductor material because this shared layer extends beyond the edges of the pixel photodiodes. Edge leakage currents are thereby reduced, and, simplified patterning of the semiconductor layer is made possible.
Each pixel may comprise a switching diode and a photodiode, with the switching diode and photodiode occupying separate areas over the substrate. The intrinsic semiconductor layer may then extend between photodiodes within a row of pixels. The intrinsic semiconductor layer may therefore be provided over a respective row conductor, and the area occupied by each pixel within the row may be maximised. Preferably, the first and second semiconductor regions also extend between adjacent photodiodes within a row of pixels. The entire diode structure may then be patterned using a single mask during the thin-film etching process.
The intrinsic semiconductor layer may alternatively extend between the photodiodes of all pixels of the array. This simplifies further the patterning of the semiconductor layer. Preferably, the second semiconductor region of the photodiodes of one column of pixels is separate from the second semiconductor region of the photodiodes of each other column of pixels. This reduces cross-talk between the columns of pixels. In this way, the second semiconductor region of the photodiodes may be patterned using the column conductors associated with the columns of pixels.
The intrinsic semiconductor region may be partially etched so that an upper portion of the intrinsic semiconductor region is patterned to correspond to the second semiconductor regions, and a lower portion of the intrinsic semiconductor region extends between the photodiodes of all pixels of the array. This partial etching of the intrinsic semiconductor region enables additional isolation between columns of pixels but also maintains the advantage of reducing edge leakage currents within the pixel photodiodes.
Preferably, each pixel comprises a bottom contact, the photodiode being disposed over the bottom contact, and a capacitor disposed over the photodiode, the capacitor having the same shape as and overlying the second semiconductor region of each pixel. The capacitor may then be etched using the same mask as for the second semiconductor region of each pixel, and this mask may effectively comprise the column conductors.
The capacitor preferably comprises a dielectric layer disposed over the second semiconductor region of each pixel, and a top contact over the dielectric layer. In this way, there is no metallic contact between the photodiode structure and the capacitor dielectric, which would otherwise interconnect the photodiodes within each column of pixels. Instead, the lateral conduction within the doped second semiconductor region is sufficiently low such that the photodiodes within each column are isolated from each other.
The image sensor may comprise a pixel area and a peripheral circuitry area, the capacitors being formed only over the pixel area. Thus, diodes are formed in the peripheral circuitry area, which enables diode-based control circuits to be formed. An area may be provided between the pixel area and the peripheral circuitry area without photodiode or capacitor layers which enables access to the base contacts, and top contacts then define connections between the diodes in the peripheral circuitry.
When the pixel photodiodes of the invention are formed using a preferred method, the photodiode comprises an intrinsic amorphous silicon layer disposed over a doped bottom conductor, the doped conductor thereby forming doped regions in the intrinsic layer which define semiconductor regions of a first doping type, and a semiconductor layer of second, opposite, doping type over the intrinsic semiconductor layer. In this way, patterning of the first semiconductor layer is not required, since the first doping type regions are formed only at the locations of the doped conductors.
The invention also provides a method of manufacturing an image sensor comprising an array of pixels, each comprising a respective photodiode, the method comprising:
depositing a conductive bottom contact layer over an insulating substrate, and patterning the contact layer with a first etching step;
depositing semiconductor layers and a capacitor dielectric layer over the patterned bottom contact layer to define a photodiode-capacitor pixel structure over the entire array; and
depositing a top contact layer over the semiconductor and capacitor dielectric layers, and patterning the top contact layer with a second etching step.
In the method of invention, there are only two essential etching steps required to fabricate the pixel array.
The photodiode layers are preferably provided over the patterned bottom contact layer, and the capacitor dielectric layer is provided over the photodiode layers.
The semiconductor layers may comprise a bottom layer of first doping type, an intrinsic layer, and a top layer of second, opposite, doping type. Alternatively, the patterned bottom contact layer may be doped, and the semiconductor layers then comprise only an intrinsic semiconductor layer and a top layer of the second doping type, the doping of the bottom contact layer giving rise to local doping of the intrinsic semiconductor layer over the patterned bottom contact layer. In either case, the capacitor dielectric layer may be etched with a third etching step using the patterned top contact layer as a mask. This etching step is therefore self-aligned and does not introduce any additional mask alignment problems. This third etching step may also be used to etch into the intrinsic semiconductor layer so that a portion of the intrinsic layer is removed.